This invention relates to a MOS technology amplifier circuit comprising a first series combination of the main current paths of a first and a second MOS transistor, the input of the amplifier circuit being coupled to the gate electrode of the first transistor, an output of the amplifier circuit being coupled to the drain electrode of the first transistor, and the gate electrode of the second transistor being coupled to its drain electrode.
A circuit of this type is known from the book entitled "Analysis and design of analog integrated circuits", 2nd Edn., by Paul R. Gray and Robert G. Meyer, published by John Wiley & Sons, more specif. FIG. 12.13(a).
The voltage gain of such an amplifier is determined by the ratios of the channel dimensions of the transistors and is approximately equal to the square root or this ratio expressed as .sqroot.k'. Since said gain ratio is unequal to one, the gate-source voltage V.sub.GS of the first transistor is unequal to that of the second transistor.
In the saturation zone the current produced by the drain electrode to a modern technology MOS transistor is in a proper approximation equal to: ##EQU1## V.sub.T is the power source electrode threshold voltage, .beta..sub.0 =.mu..sub.0 C.sub.ox. (W/L), where .mu..sub.0 is the average mobility of the load carrier in the channel region of a MOSFET transistor having a low channel field strength, C.sub.ox is the gate electrode capacitance per surface unit, W is the width and L the length of the channel region and .theta. is a mobility reduction factor occurring at higher channel field strengths.
Due to the reduction factor .theta. and the unequal gate-source voltage V.sub.GS of the two transistors, the gain is not linear, so that distortion occurs.